Semiconductor high-voltage devices

ABSTRACT

A semiconductor high-voltage device comprising a voltage sustaining layer between a n+-region and a p+-region is provided, which is a uniformly doped n(or p)-layer containing a plurality of floating p (or n)-islands. The effect of the floating islands is to absorb a large part of the electric flux when the layer is fully depleted under high reverse bias voltage so as to the peak field is not increased when the doping concentration of voltage sustaining layer is increased. Therefore, the thickness and the specific on-resistance of the voltage sustaining layer for a given breakdown voltage can be much lower than those of a conventional voltage sustaining layer with the same breakdown voltage. By using the voltage sustaining layer of this invention, various high voltage devices can be made with better relation between specific on-resistance and breakdown voltage.

FIELD OF INVENTION

This invention relates to semiconductor high voltage devices, andspecifically to semiconductor high voltage devices with voltagesustaining layer containing floating regions.

BACKGROUND OF THE INVENTION

It is well-known that in many semiconductor devices, such as VD-MOST andSIT, a high sustaining voltage always accompanies a high specificon-resistance. This is due to the fact that, for a high sustainingvoltage, thickness of a voltage sustaining layer should be large anddoping concentration of the voltage sustaining layer should be low, soas the peak field does not exceed the critical field for breakdown−E_(C), which is normally expressed by E_(C)=8.2×10⁵×V_(B) ^(−0.2) V/cmfor silicon, where V_(B) is the breakdown voltage of the voltagesustaining layer.

In a uniformly doped n-type voltage sustaining layer between p+-regionand n+-region, in order to obtain a minimum specific on-resistance at agiven breakdown voltage, a doping concentration N_(D) and a thickness Wof the voltage sustaining layer are optimized such that a maximum fieldis at p+-n-junction and its value is equal to E_(C), a minimum field isat n+-n-junction and equal to E_(C)/3. For silicon device,N _(D)=1.9×10¹⁸ ×V _(B) ^(−1.4) cm ⁻³  (1)W=1.8×10⁻² ×V _(B) ^(−1.2) μm ⁻²  (2)(see, e.g., P. Rossel, Microelectron. Reliab., vol. 24, No. 2, pp339-336, 1984).

In a VDMOST shown in FIG. 1A, a field profile in the voltage sustaininglayer at V_(B) is shown in FIG. 1B, where a slope of the field versusdistance is _(q)N_(D)/E_(s), E_(s) is the permittivity of thesemiconductor and q is the electron charge. The change of field throughthe n-region is _(q)N_(D)/E_(s), 2E_(C)/3. The relation between R_(on)and V_(B) of a n-type voltage sustaining layer is then expressed byR _(on) =W/qμμ _(n) N _(D)=0.83×10⁻⁸ ×V _(B) ^(2.5) Ω.cm ²  (3)where μ_(m) is the mobility of the electron and μ_(n)=710×V_(B) ^(0.1)cm/V.sec is used for silicon.

In order to get even lower R_(on) at a given V_(B), some research havebeen done to optimize the doping profile instead of using a uniformdoping, see: [1] C. Hu, IEEE Trans. Electron Devices, vol. ED-2, No. 3,p243 (1979); [2] V. A. K. Temple et al., IEEE Trans. Electron Devices,vol. ED-27, No. 2, p243 91980); [3] X. B. Chen, C.Hu, IEEE Trans.Electron Devices, vol. ED-27, No. 6, p985-987 (1982). However, theresults show no significant improvement.

SUMMARY OF THE INVENTION

The purpose of this invention is to provide a semiconductor high voltagedevice having a new voltage sustaining layer with better relationshipbetween R_(on) and V_(B). To achieve the above purpose, a semiconductorhigh voltage devices is provided, which comprises a substrate of a firstconductivity type, at least one region of a second conductivity type,and a voltage sustaining layer of the first conductivity type havingplurality of discrete floating (emberdded) islands of a secondconductivity between said substrate and said region of secondconductivity type.

According to this invention, and n (or p) type voltage sustaining layeris divided by (n−1) planes into n sub-layers with equal thickness, p (orn) type discrete floating islands are introduced with their geometricalcenters on such planes. The average does N_(T) of the floating islandsin each plane is about 2e_(s)Ec/3q. For silicon,N _(T)=2E _(s) E _(c)/3q=3.53.10¹² V _(B) ^(−0.2) cm ⁻²  (4)

With such a floating island, the field is reduced by an amount about2E_(C)/3 from a maximum value E_(C) at a side of the floating island toa minimum value E_(C)/3 at another side of the floating island so far asthe floating island is fully depleted. Each sub-layer is designed tosustain a voltage of V_(B1)=V_(B)/n, and to have a thickness and dopingconcentration which are almost the same as those form formulas (1) and(2) with V_(B) is replaced by V_(B1), so that when a reverse voltagewhich is about the breakdown voltage V_(B) is applied over the wholevoltage sustaining layer, the maximum field is E_(C) and the minimumfield is E_(C)/3, where the locations of the maximum field are not onlyat the p+−n (or n+−p) junction, but also at the points of each p (or n)island nearest to the n+−n (or p+−p) junction; the locations of theminimum field are not only at the n+−n (or p+−p) junction, but also atthe points of each p (or n) islands nearest to the p+−n (or n+−p)junction. An example of the structure of a VDMOST using a voltagesustaining layer of this invention with n=2 is shown in FIG. 3A and thefield profile under a reverse voltage of V_(B) is shown in FIG. 3B.Apparently, in such a condition, V_(B)=2WE_(C)/3, where W is the totalthickness of the voltage sustaining layer.

It is easy to prove that the above structured voltage sustaining layerincluding a plurality of floating regions if full depleted under areverse bias voltage about V_(B)/2. The flux due to the charges of theionized donors (or acceptors) under the p (or n) islands are almosttotally terminated by the charges of the p (or n) islands. The maximumfield is then 2E_(C)/3 and the minimum field is zero, the locations ofthe maximum field are the same as those under a reverse bias voltage ofVB.

Apparently, the p (or n) islands make the field not to be accumulatedthroughout the whole voltage sustaining layer. For a given value ofbreakdown voltage V_(B), the doping concentration N_(D) can be higherthan that in a conventional voltage sustaining layer and the specificon-resistance is much lower than that in a conventional voltagesustaining layer.

Supposed that there are n sub-layers in a voltage sustaining layer.Then, each sub-layer can sustain a voltage of V_(B)/n, where V_(B) isthe breakdown voltage of the total voltage sustaining layer. Obviously,instead of (3), the relation of R_(on) and V_(B) of this invention is$\begin{matrix}\begin{matrix}{R_{on} = {n \times 0.83 \times 10^{- 8}\left( {V_{B}/n} \right)^{2.5}{\Omega.{cm}^{2}}}} \\{= {0.83 \times 10^{- 8}{V_{B}^{2.5}/n^{1.5}}{\Omega.{cm}^{2}}}}\end{matrix} & (5)\end{matrix}$

Compared to formula (3), it can been seen that the on-resistance of avoltage sustaining layer having n sub-layers is much lower than that ofa conventional one.

The inventor has experimented and obtained remarkable results, whichshow that the on-resistance of a semiconductor device using a voltagesustaining layer with n=2 of this invention is at least lower than ½ ofthat of a conventional one with the same breakdown voltage, although thereal value of R_(on) of a voltage sustaining layer having floatingislands is a little higher than the value calculated from expression (5)when n<3, due to the effect that the current path is narrowed by thep-type floating islands. Besides, for minimizing R_(on), the optimumvalue of N_(T) is slightly different with the expression (4), due tothat the negative charges of p-type floating islands are concentrated inthe p-regions instead of being uniformly distributed on a plane, whereasthese negative charges are used to absorb the flux of ionized donorsbelow that plane.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is the schematic diagram of the VDMOST of prior art, where FIG.1A shows the structure and FIG. 1B shows the field profile.

FIG. 2 shows a voltage sustaining layer structure of this invention,where FIG. 2A shows a voltage sustaining layer structure with islands inone plane. FIGS. 2B and 2C show the structures of the voltage sustaininglayer with the floating islands in two planes.

FIG. 3 shows the structure and the field profile of a VDMOST with thevoltage sustaining layer of this invention. In FIG. 3A, the voltagesustaining layer of FIG. 2A is used. The field profile of this structureunder a reverse voltage of V_(B) is shown in FIG. 3B. In FIG. 3C, avoltage sustaining layer of FIG. 2C is used.

FIG. 4 shows the structure of an IGBT with a voltage sustaining layer ofthis invention. In FIG. 4A, a voltage sustaining layer of FIG. 2A isused. In FIG. 4B, a voltage sustaining layer of FIG. 2C is used.

FIG. 5 shows a structure of a RMOST with the voltage sustaining layer ofthis invention shown in FIG. 2A.

FIG. 6 shows a structure of a bipolar junction transistor with thevoltage sustaining layer of this invention shown in FIG. 2A.

FIG. 7 shows a structure of a SIT with the voltage sustaining layer ofthis invention shown in FIG. 2A.

All the structures schematically shown in the figures arecross-sectional view. In FIGS. 3-7, the same numeral designates similarpart of a high voltage semiconductor device, where, 1 designates p (orn) island in the voltage sustaining layer; 3 designates n+ (or p+)substrate; 4 designates p (or n) source body; 5 designates n+ (or p+)source; 6 designates p+(or n+) substrate; 7 designates n (or p) bufferlayer; 8 designates p+ (or n+) outer base of BJT; 9 designates p+ (orn+) grid of SIT; and shaded regions designate oxide regions.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 2 shows several structures of a voltage sustaining layer accordingto the invention.

In FIG. 2A, a voltage sustaining layer with p (or n) islands in a planeis shown (i.e., n=2, two sub-layers). In FIG. 2B, a voltage sustaininglayer with p (or n) islands disposed in two planes is shown (i.e., n=3,three sub-layers), where each island in the upper plane is verticallyarranged over a corresponding island in the lower plane. FIG. 2C showsanother voltage sustaining layer with two planes of p (or n) islands(n=3), wherein each of islands in the upper plane is vertically arrangedin the middle of two neighboring islands in the lower plane.

The horizontal layout of the voltage sustaining layer than be eitherinterdigitated (finger), or hexagonal (cell), or rectangular (cell). Inall the figures of schematic cross-sectional view of the structures,only one or two units (fingers or cells) of the voltage sustaining layerare shown.

The voltage sustaining layer of this invention can be used in many highvoltage devices.

1) High Voltage Diode

This can be simply realized by forming two electrodes on the p+-regionand the n+-region in any of structures shown in FIG. 2.

2) High Voltage (or Power) VDMOST

FIG. 3A shows a structure of a VDMOST using the voltage sustaining layerwith a plurality of floating islands disposed in one plane, i.e. n=2.FIG. 3B shows the field profile along a line through a center of anislands in the voltage sustaining layer and perpendicular to said planesin FIG. 3A. FIG. 3C shows a structure of a VDMOST using a voltagesustaining layer with islands in two planes, i.e. n=3.

The turn-off process of a resultant device is almost as fast as aconventional VDMOST. The turn-on process is like the turn-off process ofa conventional IGBT, which consists of a fast stage and a long tail. Thelong tail is due to that the p (or n) islands needs to be charged.

3) High Voltage (or Power) IGBT

FIG. 4A shows a structure of an IGBT using a voltage sustaining layerwith n=2. FIG. 4B shows a structure of an IGBT using a voltagesustaining layer with n=3. In order to improve the turn-on process of aVDMOST with the voltage sustaining layer of this invention, only a fewamount of minorities is needed to charge the islands in the voltagesustaining layer. This can be done by using a IGBT structure with a verlow injection by the inventor that an injection ratio of less than 0.1is enough to make the turn-on process to be almost as fast as theturn-off process and results no long tail. The low injection ratio makesthe device operate dominantly by the majority carriers.

4) High Voltage (or Power) RMOST

FIG. 5 shows a structure of an RMOST using a voltage sustaining layer ofthis invention, where n=2.

5) High Voltage (or Power) BJT

FIG. 6 shows a structure of a bipolar junction transistor using avoltage sustaining layer of this invention, where n=2.

6) High Voltage (or Power)SIT

FIG. 7 shows a structure of a static induction transistor using avoltage sustaining layer of this invention, where n=2.

The design references of a voltage sustaining layer of this inventionmay be calculated according to above formulas for calculating E_(C) andthe average does of the islands in a plane. For example, at first, avalue of a desirable breakdown voltage V_(B) is determined, and thevalue of E_(C) is calculated from the determined E_(C). Then, from thetechnology achievable number of sub-layers n, the lateral size of a unitand the width of the islands in a plane, the number of impurity atoms ineach island is calculated. The calculated values can be used as thereference values for simulation in CAD is more accurate values areneeded.

An example of process for making a vertical n-IGBT using the voltagesustaining layer of this invention is stated briefly as follows:

-   -   First step: preparing a wafer of a p+-substrate having an        n+-buffer on it.    -   Second step: forming a n-epilayer on said wafer;    -   Third step: growing a thin oxide layer on the epilayer and        forming openings by photo-lithograph;    -   Fourth step: implanting boron through the openings for making        p-islands and then removing the oxide layer;    -   Fifth step: repeat (n−1) times of second step to fourth step.

The following steps are all the same as fabricating a conventional IGBT.

Although the invention has been described and illustrated with referenceto specific embodiments thereof, it is not intended that the inventionbe limited to these illustrative embodiments. Those skilled in the artwill recognized that modifications and variations can be made withoutdeparting from the spirit of the invention. Therefore, it is intendedthat this invention encompass all such variations and modifications asfall within the scope of the appended claims.

1-19. (canceled)
 20. A semiconductor device comprising: a substrate of afirst conductivity type; a first region of a second conductivity type; avoltage sustaining layer of the first conductivity type located betweenthe substrate and the first region; and an embedded region of the secondconductivity type located between the substrate and the first region,the embedded region being entirely embedded within the voltagesustaining layer and spaced apart from the substrate and the firstregion by an approximate equal distance. 21-28. (Canceled)
 29. Thesemiconductor device according to claim 20 further comprising: a secondembedded region of the second conductivity type located between thesubstrate and the first region, the second embedded region beingentirely embedded within the voltage sustaining layer and spaced apartfrom the substrate and the first region by an approximate equal distanceand spaced apart from the other embedded region of the secondconductivity type.
 30. A semiconductor power device comprising: asubstrate of a first conductivity type; a first region of a secondconductivity type; a voltage sustaining layer of the first conductivitytype located between the substrate and the first region, the voltagesustaining layer having a width, W; and a plurality of m regions of thesecond conductivity type located in alignment within the voltagesustaining layer between the substrate and the first region, and a firstmember of the plurality of m embedded regions being centered on a planespaced apart from the substrate by an approximate distance of W/n, and asecond member being centered on a second plane spaced apart from thefirst region by an approximate distance of W/n, and wherein m and n arepositive integers.
 31. The semiconductor device according to claim 30further comprising: a second plurality of P regions of the secondconductivity type located within the voltage sustaining layer betweenthe substrate and the first region and in parallel alignment with theplurality of m regions, and a first member of the plurality of p regionsbeing centered on a third planed spaced apart from the substrate by anapproximate distance of 2W/n and a second member of the plurality of Pregions being spaced apart from the first region by an approximatedistance of W/n and wherein P is a positive integer and is less than m.32. The semiconductor power device according to claim 30 wherein thesemiconductor is a diode and the substrate is a cathode and the firstregion is an anode.
 33. The semiconductor according to claim 30 whereinthe semiconductor device is a VDMOST and the substrate is a drain andthe first region further includes a source region.
 34. The semiconductordevice according to claim 30 wherein the first member and the secondmember are between the substrate and the first region.
 35. Thesemiconductor device according to claim 34 further including a thirdregion also spaced apart from the substrate and also spaced apart fromthe first and second members.
 36. The semiconductor device according toclaim 35 wherein the first member and third member are in parallelalignment with the substrate and spaced apart by a predetermineddistance and the second member is non aligned with the first member andthe substrate.
 37. The semiconductor power device according to claim 30further including a third member of the plurality of embedded regionsalso spaced apart from the first region by an approximate distance ofW/n and spaced apart from the first and second members.
 38. Thesemiconductor power device according to claim 37 wherein the thirdmember and second member being in parallel alignment with each other andthe first region, and spaced apart by a predetermined distance, and thefirst member being in perpendicular alignment with the first region andsubstrate.
 39. A semiconductor power device comprising: a first layer ofa first conductivity type of a first concentration; a second layer ofthe first conductivity type of a second concentration located on top ofthe first layer; a first region of a second conductivity type located ona top surface of the second layer and extending into the second layertowards the first layer to a predetermined dept; a voltage sustaininglayer of the first conductivity type located between the first layer anda boundary between the second layer and the first region at thepredetermined depth; and an embedded region of the second conductivitytype embedded within the voltage sustaining layer and spaced apart fromthe first layer and the boundary by an approximate equal distance. 40.The semiconductor device according to claim 39 further comprising: asecond region of the second conductivity type located on a top surfaceof the second layer and extending into the second layer towards thefirst layer to the predetermined dept, the first region and the secondregion being spaced apart from each other; and a channel region locatedbetween the first region and the second region.
 41. The semiconductordevice according to claim 40 wherein the embedded region is in alignmentbetween the channel region and the first layer.
 42. The semiconductordevice according to claim 39 further comprising: a second embeddedregion of the second conductivity type embedded within the voltagesustaining layer and spaced apart from the embedded region and spacedapart from the first layer and the boundary.
 43. The semiconductordevice according to claim 42 further comprising: a second region of thesecond conductivity type located on a top surface of the second layerand extending into the second layer towards the first layer to thepredetermined dept, the first region and the second region being spacedapart from each other; and a channel region located between the firstregion and the second region.
 44. The semiconductor device according toclaim 42 wherein the embedded region is in alignment between the firstregion and the first layer and the second embedded region is inalignment between the second region and the first layer.
 45. Asemiconductor device comprising: a first layer of a first conductivitytype of a first concentration; a second layer of the first conductivitytype of a second concentration located on top of the first layer; afirst region of a second conductivity type located on a top surface ofthe second layer and extending into the second layer towards the firstlayer to a predetermined dept; a voltage sustaining layer of the firstconductivity type located between the first layer and a boundary betweenthe second layer and the first region at the predetermined depth, thevoltage sustaining layer having a width, W; and a plurality of membedded regions of the second conductivity type located between thefirst layer and the first region, the plurality of m embedded regionsbeing entirely embedded within the voltage sustaining layer and a firstmember of the plurality of m third embedded regions being spaced apartfrom the first layer by an approximate distance of W/n and a secondmember being spaced apart from the boundary by the approximate distanceof W/n, and wherein m and n are positive integers.
 46. The semiconductordevice according to claim 45 further comprising: a second region of thesecond conductivity type located on a top surface of the second layerand extending into the second layer towards the first layer to thepredetermined dept, the first region and the second region being spacedapart from each other; and a channel region located between the firstregion and the second region.
 47. The semiconductor device according toclaim 46 wherein the first member of the plurality of m embedded regionsbeing in alignment with the first region and the first layer and thesecond member of the plurality of m embedded regions being in alignmentwith the second region and the first layer.
 48. The semiconductor deviceaccording to claim 46 further comprising: the first member of theplurality of m embedded regions being in vertical alignment with thefirst region and the first layer; the second member of the plurality ofm embedded regions being in vertical alignment with the channel and thefirst layer; and a third member of the plurality of m embedded regionsbeing spaced apart from the first layer by approximate distance of W/nand in vertical alignment with the second region and the first layer.49. A method of manufacturing a semiconductor device comprising thesteps of: preparing a semiconductor wafer with a substrate of a firstconductivity type; forming a first epitaxial layer of the firstconductivity type on the substrate, the epitaxial layer having a firstthickness; growing an oxide layer on the first epitaxial layer; maskingthe oxide layer; ion implanting to create at least one embedded islandof dopant of the second conductivity type in the first epitaxial layer;removing the oxide layer; forming a final epitaxial layer of the firstconductivity type on the first epitaxial layer, the second epitaxiallayer having the first thickness plus a thickness equal to the depth ofthe embedded islands of the second conductivity type; growing an oxidelayer on the second epitaxial layer; masking the oxide layer; and ionimplanting to create at least a single embedded region of the secondconductivity type extending into the second epitaxial layer.
 50. Amethod of manufacturing a semiconductor device comprising the steps of:preparing a semiconductor wafer with a substrate of a first conductivitytype; forming a first epitaxial layer of the first conductivity type onthe substrate, the epitaxial layer having a first thickness; growing anoxide layer on the first epitaxial layer; masking the oxide layer; ionimplanting to create at least one embedded island of dopant of thesecond conductivity type in the first epitaxial layer; removing theoxide layer; forming a second epitaxial layer of the first conductivitytype on the first epitaxial layer, the second epitaxial layer having thefirst thickness plus a thickness equal to the depth of the body regionof a VDMOS FET; growing an oxide layer on the second epitaxial layer;masking the oxide layer; and ion implanting to create at least oneembedded region of the second conductivity type extending into thesecond epitaxial layer.
 51. A method of manufacturing a semiconductordevice comprising the steps of: preparing a semiconductor wafer with asubstrate of a first conductivity type having a buffer layer of thefirst conductivity type; forming a first epitaxial layer of the firstconductivity type on the substrate, the epitaxial layer having a firstthickness; growing an oxide layer on the first epitaxial layer; maskingthe oxide layer; ion implanting to create at least one embedded islandof dopant of the second conductivity type in the first epitaxial layer;removing the oxide layer; forming a second epitaxial layer of the firstconductivity type on the first epitaxial layer, the second epitaxiallayer having the first thickness plus a thickness equal to the depth ofthe body region of an IGBT; growing an oxide layer on the secondepitaxial layer; masking the oxide layer; and ion implanting to createembedded at least one embedded region of the second conductivity typeextending into the second epitaxial layer.